An increase in the integration and functionality of semiconductor devices has been accompanied by the mounting of analog and digital circuits on a single semiconductor substrate constituting a semiconductor device.
When analog and digital circuits are mounted on the same substrate, there are instances where noise generated by the digital circuit penetrates into the analog circuit through the substrate and hampers operation of the analog circuit.
It has been proposed to provide a guard ring between the analog and digital circuits in order to solve this problem.
By way of example, as illustrated in FIG. 9 showing a semiconductor device 200 according to the prior art, it has been proposed to form a P-type semiconductor substrate 201 to have an N-well 202 that constructs an analog-circuit forming region and an N-well 203 that constructs a digital-circuit forming region, and to form a guard ring 204 in the N-well 203 of the digital-circuit forming region (see the specification of Japanese Patent Kokai Publication No. JP-P2001-345428A, referred to as “Patent Document 1” below).
An analog circuit 205 is formed in the N-well 202, and a digital circuit 206 is formed in the N-well 203. According to Patent Document 1, propagation of noise from the digital-circuit forming region to the analog-circuit forming region can be prevented by adjusting the depth of the guard ring 204.
Further, as illustrated in FIG. 10 showing a semiconductor device 100 according to the prior art, it has been proposed to form a P-type semiconductor substrate 101 to have a P-well 102 provided with an NMOS transistor 103 and an N-well 105 provided with a PMOS transistor 104, and to provide an N-type guard ring 106 that is in contact with the P-well 102 and N-well 105 (see the specification of Japanese Patent Kokai Publication No. JP-P2002-76289A, referred to as “Patent Document 2” below). Reference numerals 107, 108 in FIG. 10 denote guard rings.
Since the semiconductor device 200 of Patent Document 1 shown in FIG. 9 is such that the P-type semiconductor substrate 201 is formed to have the N-well 202 that constructs the analog-circuit forming region and the N-well 203 that constructs the digital-circuit forming region, PN junctions are formed between the N-wells 202, 203 and the P-type semiconductor substrate 201. Consequently, the arrangement is such that it is difficult for noise from the digital-circuit forming region to propagate to the analog-circuit forming region.
However, Patent Document 1 does not give any consideration with regard to propagation of noise in a case where the N-well 202 of the analog-circuit forming region or the N-well 203 of the digital-circuit forming region is changed to a P-well and the PN junction is no longer formed. This means that with the structure described in Patent Document 1, it is difficult to suppress the propagation of noise in a case where the N-well 202 of the analog-circuit forming region or the N-well 203 of the digital-circuit forming region is changed to a P-well.
On the other hand, in the semiconductor device 100 described in Patent Document 2 shown in FIG. 10, the P-well 102 is formed in the P-type semiconductor substrate 101. Since the N-type guard ring 106 that contacts the P-well 102 is formed between the P-well 102 and the N-well 105, a PN junction is formed between the P-well 102 and the guard ring 106 and it is presumed that the propagation of noise can be suppressed to a certain extent.
In recent years, however, there has been increasing demand for more reliable suppression of noise propagation, especially for the prevention of noise propagation in the high-frequency region. With the semiconductor device 100, however, it is difficult to satisfy such a demand.
The inventors have conjectured that a large junction capacitance between the N-type guard ring 106 and P-well 102 in the semiconductor device 100 is the reason why propagation of noise (especially propagation of noise in the high-frequency region) cannot be suppressed satisfactorily.